文章插图
数字逻辑与Verilog设计（第3版）【第3版 数字逻辑与Verilog设计】《数字逻辑与Verilog设计（第3版）》是2014年清华大学出版社出版的图书 。
基本介绍书名：数字逻辑与Verilog设计（第3版）
ISBN：9787302366850
定价：99.00元
出版社：清华大学出版社
出版时间：2014-7-8
装帧：平装
图书简介本书共包括11章正文和两篇附录 。为了让读者了解传统的人工进行数字设计的基本理论，前六章主要还是介绍数字逻辑的基础，且此部分内容可以作为一个学期的数字逻辑设计导论课程 。由于数字系统的规模越来越大，採用计算机辅助设计工具来完成数字电路的设计势在必行，因此本书从第2章开始就将相关知识融入到基础理论中，让读者能在阅读和学习过程中潜移默化地掌握Verilog代码编写风格，达到事半功倍的效果 。目录Chapter 1Introduction11.1Digital Hardware21.1.1Standard Chips41.1.2Programmable Logic Devices51.1.3CustomDesigned Chips51.2The Design Process61.3Structure of a Computer81.4Logic Circuit Design in This Book81.5Digital Representation of Information111.5.1Binary Numbers121.5.2Conversion between Decimal andBinary Systems131.5.3ASCII Character Code141.5.4Digital and Analog Information161.6Theory and Practice16Problems18References19Chapter 2Introduction to LogicCircuits212.1Variables and Functions222.2Inversion252.3Truth Tables262.4Logic Gates and Networks272.4.1Analysis of a Logic Network292.5Boolean Algebra332.5.1The Venn Diagram372.5.2Notation and Terminology422.5.3Precedence of Operations43第1章绪论11.1数字硬体21.1.1标準晶片41.1.2可程式逻辑器件51.1.3定製晶片51.2设计过程61.3计算机结构81.4本书中的逻辑电路设计81.5信息的数字表示111.5.1二进制数121.5.2十进制和二进制系统之间的转换131.5.3ASCII字元码141.5.4数字和模拟信息161.6理论和实践16习题18参考文献19第2章逻辑电路导论212.1变数和函式222.2反相252.3真值表262.4逻辑门和网路272.4.1逻辑网路的分析292.5布尔代数332.5.1维恩图372.5.2符号和术语422.5.3操作的优先权432.6Synthesis Using AND, OR, and NOTGates432.6.1SumofProducts and ProductofSums Forms482.7NAND and NOR Logic Networks542.8Design Examples592.8.1ThreeWay Light Control592.8.2Multiplexer Circuit602.8.3Number Display632.9Introduction to CAD Tools642.9.1Design Entry642.9.2Logic Synthesis662.9.3Functional Simulation672.9.4Physical Design672.9.5Timing Simulation672.9.6Circuit Implementation682.9.7Complete Design Flow682.10Introduction to Verilog682.10.1Structural Specification of LogicCircuits702.10.2Behavioral Specification of LogicCircuits722.10.3Hierarchical Verilog Code762.10.4How NOT to Write Verilog Code782.11Minimization and Karnaugh Maps782.12Strategy for Minimization872.12.1Terminology872.12.2Minimization Procedure892.13Minimization of ProductofSums Forms912.14Incompletely Specified Functions942.15MultipleOutput Circuits962.16Concluding Remarks101 2.17Examples of Solved Problems101Problems111References1202.6用与、或和非门进行综合432.6.1与或和或与形式482.7与非和或非逻辑网路542.8设计实例592.8.1三路灯光控制592.8.2多路选择器电路602.8.3数字显示632.9CAD工具简介642.9.1设计输入642.9.2逻辑综合662.9.3功能仿真672.9.4物理设计672.9.5时序仿真672.9.6电路实现682.9.7完整的设计流程682.10Verilog简介682.10.1逻辑电路的结构描述702.10.2逻辑电路的行为描述722.10.3层次化Verilog代码762.10.4如何不写Verilog代码782.11化简和卡诺图782.12化简策略872.12.1术语872.12.2化简过程892.13或与形式的最简912.14不完全确定函式942.15多输出电路962.16小结1012.17问题求解案例101习题111参考文献120Chapter 3Number Representation andArithmetic Circuits1213.1Positional Number Representation1223.1.1Unsigned Integers1223.1.2Octal and HexadecimalRepresentations1233.2Addition of Unsigned Numbers1253.2.1Decomposed FullAdder1293.2.2RippleCarry Adder1293.2.3Design Example1303.3Signed Numbers1323.3.1Negative Numbers1333.3.2Addition and Subtraction1353.3.3Adder and Subtractor Unit1383.3.4RadixComplement Schemes1393.3.5Arithmetic Overflow1433.3.6Performance Issues1453.4Fast Adders1453.4.1CarryLookahead Adder1463.5Design of Arithmetic Circuits Using CADTools1513.5.1Design of Arithmetic Circuits Using Schematic Capture1513.5.2Design of Arithmetic Circuits UsingVerilog1523.5.3Using Vectored Signals1553.5.4Using a Generic Specification1563.5.5Nets and Variables in Verilog1583.5.6Arithmetic AssignmentStatements1593.5.7Module Hierarchy in VerilogCode1633.5.8Representation of Numbers in VerilogCode1663.6Multiplication1673.6.1Array Multiplier for UnsignedNumbers1673.6.2Multiplication of SignedNumbers1693.7Other Number Representations1703.7.1FixedPoint Numbers1703.7.2FloatingPoint Numbers1723.7.3BinaryCodedDecimalRepresentation1743.8Examples of Solved Problems178Problems184References188Chapter 4CombinationalCircuit BuildingBlocks1894.1Multiplexers1904.1.1Synthesis of Logic Functions Using Multiplexers1934.1.2Multiplexer Synthesis Using ShannonsExpansion1964.2Decoders2014.2.1Demultiplexers2034.3Encoders2054.3.1Binary Encoders2054.3.2Priority Encoders2054.4Code Converters2084.5Arithmetic Comparison Circuits2084.6Verilog for Combinational Circuits2104.6.1The Conditional Operator2104.6.2The IfElse Statement2124.6.3The Case Statement2154.6.4The For Loop221 4.6.5Verilog Operators2234.6.6The Generate Construct2284.6.7Tasks and Functions229第3章数的表示和算术电路1213.1数位表示法1223.1.1无符号整数1223.1.2八进制数和十六进制数的表示1233.2无符号数的加法1253.2.1全加器的分解1293.2.2行波进位加法器1293.2.3设计实例1303.3有符号数1323.3.1负数1333.3.2加法和减法1353.3.3加法器和减法器单元1383.3.4基数补码方案1393.3.5算术溢出1433.3.6性能问题1453.4快速加法器1453.4.1超前进位加法器1463.5用CAD工具设计算术电路1513.5.1用原理图编辑工具设计算术电路1513.5.2用Verilog设计算术电路1523.5.3用向量信号1553.5.4用自动生成语句1563.5.5Verilog中的线网和变数1583.5.6算术赋值语句1593.5.7Verilog中的模组层次化1633.5.8Verilog中数的表示1663.6乘法1673.6.1无符号数的阵列乘法1673.6.2有符号数的乘法1693.7其他数的表示1703.7.1定点数1703.7.2浮点数1723.7.3二进制编码的十进制数表示1743.8问题求解案例178习题184参考文献188第4章组合电路构件块1894.1多路选择器1904.1.1用多路选择器进行逻辑函式综合1934.1.2用香农展开进行多路选择器综合1964.2解码器2014.2.1多路分解器2034.3编码器2054.3.1二进制编码器2054.3.2优先编码器2054.4码制转换器2084.5算术比较电路2084.6用Verilog表示组合电路2104.6.1条件操作符2104.6.2ifelse语句2124.6.3case语句2154.6.4for循环语句2214.6.5Verilog操作符2234.6.6生成结构2284.6.7任务和函式2294.7Concluding Remarks2324.8Examples of Solved Problems233Problems243References246Chapter 5FlipFlops, Registers, andCounters247 5.1Basic Latch2495.2Gated SR Latch2515.2.1Gated SR Latch with NANDGates2535.3Gated D Latch2535.3.1Effects of Propagation Delays2555.4EdgeTriggered D FlipFlops2565.4.1MasterSlave D FlipFlop2565.4.2Other Types of EdgeTriggeredD FlipFlops2585.4.3D FlipFlops with Clear andPreset2605.4.4FlipFlop Timing Parameters2635.5T FlipFlop2635.6JK FlipFlop2645.7Summary of Terminology2665.8Registers2675.8.1Shift Register2675.8.2ParallelAccess Shift Register2675.9Counters2695.9.1Asynchronous Counters2695.9.2Synchronous Counters2725.9.3Counters with Parallel Load2765.10Reset Synchronization2785.11Other Types of Counters2805.11.1BCD Counter2805.11.2Ring Counter2805.11.3Johnson Counter2835.11.4Remarks on Counter Design2835.12Using Storage Elements with CADTools2845.12.1Including Storage Elements inSchematics2845.12.2Using Verilog Constructs for StorageElements2855.12.3Blocking and NonBlockingAssignments2885.12.4NonBlocking Assignments forCombinational Circuits2935.12.5FlipFlops with ClearCapability2935.13Using Verilog Constructs for Registersand Counters2955.13.1FlipFlops and Registers withEnable Inputs3005.13.2Shift Registers with Enable Inputs3025.14Design Example3025.14.1Reaction Timer3025.14.2Register Transfer Level (RTL)Code3095.15Timing Analysis of FlipflopCircuits3105.15.1Timing Analysis with ClockSkew3125.16Concluding Remarks3145.17Examples of Solved Problems315Problems321References329Chapter 6Synchronous SequentialCircuits3316.1Basic Design Steps3336.1.1State Diagram3334.7小结2324.8问题求解案例233习题243参考文献246第5章触发器、暂存器和计数器2475.1基本锁存器2495.2门控SR锁存器2515.2.1用与非门实现的门控SR锁存器2535.3门控D锁存器2535.3.1传输延时的影响2555.4边沿触发的D触发器2565.4.1主从D触发器2565.4.2其他类型的边沿触发的D触发器2585.4.3带清零和置位的D触发器2605.4.4触发器的时间参数2635.5T触发器2635.6JK触发器2645.7术语小结2665.8暂存器2675.8.1移位暂存器2675.8.2并行存取的移位暂存器2675.9计数器2695.9.1异步计数器2695.9.2同步计数器2725.9.3可并行置数的计数器2765.10同步复位2785.11其他类型的计数器2805.11.1BCD计数器2805.11.2环形计数器2805.11.3约翰森（Johnson）计数器2835.11.4计数器设计小结2835.12CAD工具中存储单元的使用2845.12.1在原理图中加入存储单元2845.12.2用Verilog代码实现存储单元2855.12.3阻塞和非阻塞赋值2885.12.4组合电路的非阻塞赋值2935.12.5具有清零功能的触发器2935.13用Verilog代码实现暂存器和计数器2955.13.1具有使能输入的触发器和暂存器3005.13.2具有使能输入的移位 暂存器3025.14设计案例3025.14.1反应计时器3025.14.2暂存器传输级（RTL）代码3095.15触发器电路的时序分析3105.15.1有时钟漂移的时序分析3125.16小结3145.17问题求解案例315习题321参考文献329第6章同步时序电路3316.1基本设计步骤3336.1.1状态图3336.1.2State Table3356.1.3State Assignment3366.1.4Choice of FlipFlops and Derivationof NextState and OutputExpressions3376.1.5Timing Diagram3396.1.6Summary of Design Steps3406.2StateAssignment Problem3446.2.1OneHot Encoding3476.3Mealy State Model3496.4Design of Finite State Machines UsingCAD Tools3546.4.1Verilog Code for MooreTypeFSMs3556.4.2Synthesis of Verilog Code3566.4.3Simulating and Testing theCircuit3586.4.4Alternative Styles of VerilogCode3596.4.5Summary of Design Steps WhenUsing CAD Tools3606.4.6Specifying the State Assignment inVerilog Code3616.4.7Specification of Mealy FSMs UsingVerilog3636.5Serial Adder Example3636.5.1MealyType FSM for SerialAdder3646.5.2MooreType FSM for SerialAdder3676.5.3Verilog Code for the SerialAdder3706.6State Minimization3726.6.1Partitioning MinimizationProcedure3746.6.2Incompletely Specified FSMs3816.7Design of a Counter Using the Sequential Circuit Approach3836.7.1State Diagram and State Table for aModulo8Counter3836.7.2State Assignment3846.7.3Implementation Using DType FlipFlops3856.7.4Implementation Using JKType FlipFlops3866.7.5Example—A Different Counter3906.8FSM as an Arbiter Circuit3936.9Analysis of Synchronous SequentialCircuits3976.10Algorithmic State Machine (ASM)Charts4016.11Formal Model for SequentialCircuits4056.12Concluding Remarks4076.13Examples of Solved Problems407Problems416References420Chapter 7Digital System Design4217.1Bus Structure4227.1.1Using TriState Drivers to Implementa Bus4227.1.2Using Multiplexers to Implementa Bus4247.1.3Verilog Code for Specification of BusStructures4267.2Simple Processor4297.3A BitCounting Circuit4417.4ShiftandAdd Multiplier4467.5Divider4557.6Arithmetic Mean4666.1.2状态表3356.1.3状态分配3366.1.4触发器的选择以及次态和输出表达式的推导3376.1.5时序图3396.1.6设计步骤小结3406.2状态分配问题3446.2.1单热编码3476.3米利状态模型3496.4用CAD工具设计有限状态机3546.4.1摩尔型有限状态机的Verilog代码3556.4.2Verilog代码的综合3566.4.3仿真和测试该电路3586.4.4另一种风格的Verilog代码3596.4.5用CAD工具的设计步骤 小结3606.4.6在Verilog代码中进行状态分配3616.4.7用Verilog代码来描述米利有限状态机3636.5串列加法器举例3636.5.1串列加法器的米利型有限状态机3646.5.2串列加法器的摩尔型有限状态机3676.5.3串列加法器的Verilog代码3706.6状态化简3726.6.1化简过程的划分3746.6.2不完全确定的有限状态机3816.7用时序电路方法设计计数器3836.7.1模8计数器的状态图和状态表3836.7.2状态分配3846.7.3用D触发器实现3856.7.4用JK触发器实现3866.7.5案例——一个不一样的计数器3906.8用作仲裁器电路的有限状态机3936.9同步时序电路分析3976.10算法状态机（ASM）图4016.11时序电路的形式化模型4056.12小结4076.13问题求解案例407习题416参考文献420第7章数字系统设计4217.1汇流排结构4227.1.1用三态驱动器实现汇流排4227.1.2用多路选择器实现汇流排4247.1.3汇流排结构的Verilog代码描述4267.2简单处理器4297.3位计数电路4417.4移位相加实现的乘法器4467.5除法器4557.6算术平均4667.7Sort Operation4707.8Clock Synchronization and TimingIssues4787.8.1Clock Distribution4787.8.2FlipFlop Timing Parameters4817.8.3Asynchronous Inputs toFlipFlops4827.8.4Switch Debouncing4837.9Concluding Remarks485Problems485References489Chapter 8Optimized Implementation ofLogic Functions4918.1Multilevel Synthesis4928.1.1Factoring4938.1.2Functional Decomposition4968.1.3Multilevel NAND and NORCircuits5028.2Analysis of Multilevel Circuits5048.3Alternative Representations of Logic Functions5108.3.1Cubical Representation5108.3.2Binary Decision Diagrams5148.4Optimization Techniques Based on CubicalRepresentation5208.4.1A Tabular Method forMinimization5218.4.2A Cubical Technique forMinimization5298.4.3Practical Considerations5368.5Concluding Remarks5378.6Examples of Solved Problems537Problems546References549Chapter 9Asynchronous SequentialCircuits5519.1Asynchronous Behavior5529.2Analysis of Asynchronous Circuits5569.3Synthesis of Asynchronous Circuits5649.4State Reduction5779.5State Assignment5929.5.1Transition Diagram5959.5.2Exploiting Unspecified NextStateEntries5989.5.3State Assignment Using AdditionalState Variables6029.5.4OneHot State Assignment6079.6Hazards6089.6.1Static Hazards6099.6.2Dynamic Hazards6139.6.3Significance of Hazards6149.7A Complete Design Example6169.7.1The VendingMachineController6169.8Concluding Remarks6219.9Examples of Solved Problems623Problems631References635Chapter 10Computer Aided DesignTools63710.1Synthesis63810.1.1Netlist Generation63810.1.2Gate Optimization63810.1.3Technology Mapping64010.2Physical Design644 10.2.1Placement64610.2.2Routing64710.2.3Static Timing Analysis6487.7排序操作4707.8时钟同步和时序问题4787.8.1时钟偏差4787.8.2触发器的时序参数4817.8.3触发器的异步输入4827.8.4开关抖动4837.9小结485习题485参考文献489第8章逻辑函式的最佳化实现4918.1多级综合4928.1.1提取公因子4938.1.2函式分解4968.1.3多级与非和或非电路5028.2多级电路的分析5048.3逻辑函式的替代表示5108.3.1立方体表示5108.3.2二进制决策图5148.4基于立方体表示的最佳化技术5208.4.1化简的列表法5218.4.2立方体化简技术5298.4.3实际问题考虑5368.5小结5378.6问题求解案例537习题546参考文献549第9章异步时序电路5519.1异步行为5529.2异步电路分析5569.3异步电路综合5649.4状态化简5779.5状态分配5929.5.1转移图5959.5.2未指定次态项的利用5989.5.3用附加状态进行的状态分配6029.5.4单热状态分配6079.6冒险6089.6.1静态冒险6099.6.2动态冒险6139.6.3冒险的意义6149.7一个完整的设计实例6169.7.1自动售货机控制器6169.8小结6219.9问题求解案例623习题631参考文献635第10章计算机辅助设计工具63710.1综合63810.1.1网表生成63810.1.2门最佳化63810.1.3技术映射64010.2物理设计64410.2.1布局64610.2.2布线64710.2.3静态时序分析64810.3Concluding Remarks650References651Chapter 11Testing of Logic Circuits65311.1Fault Model65411.1.1Stuckat Model65411.1.2Single and Multiple Faults65511.1.3CMOS Circuits65511.2Complexity of a Test Set65511.3Path Sensitizing65711.3.1Detection of a Specific Fault659 11.4Circuits with Tree Structure66111.5Random Tests66211.6Testing of Sequential Circuits66511.6.1Design for Testability66511.7内建自测试66911.7.1内建逻辑块观察器67311.7.2签字分析67511.7.3边界扫描67611.8印製电路板67611.8.1PCB测试67811.8.2测试仪器67911.9小结680习题680参考文献683附录A数的表示和算术电路685A.1Verilog代码中的文档686A.2空白符686A.3Verilog代码中的信号686A.4标识符687A.5信号值、数值和参数687A.5.1参数688A.6线网和变数类型688A.6.1线网688A.6.2变数689A.6.3存储器690A.7操作符690A.8Verilog模组692A.9门实例化694A.10并行语句696A.10.1连续赋值696A.10.2使用参数697A.11过程语句698A.11.1Always和Initial块698A.11.2ifelse语句700A.11.3语句顺序701A.11.4case语句702A.11.5Casez和Casex语句703A.11.6Loop语句704A.11.7组合电路的阻塞和非阻塞赋值对比708A.12使用子电路709A.12.1子电路参数710A.12.2生成能力712A.13函式和任务713A.14时序电路716A.14.1门控D锁存器717A.14.2D触发器717A.14.3带复位的触发器718A.14.4暂存器718A.14.5移位暂存器720A.14.6计数器721A.14.7时序电路实例722A.14.8摩尔型有限状态机723A.14.9MealyTypeFiniteStateMachines724A.15GuidelinesforWritingVerilogCode725A.16ConcludingRemarks731References731AppendixBImplementationTechnology733B.1TransistorSwitches734B.2NMOSLogicGates736B.3CMOSLogicGates739 B.3.1SpeedofLogicGateCircuits746B.4NegativeLogicSystem747B.5StandardChips749B.5.17400SeriesStandardChips749B.6ProgrammableLogicDevices753B.6.1ProgrammableLogicArray(PLA)754B.6.2ProgrammableArrayLogic(PAL)757B.6.3ProgrammingofPLAsandPALs759B.6.4ComplexProgrammableLogicDevices(CPLDs)761B.6.5FieldProgrammableGateArrays764B.7CustomChips,StandardCells,andGateArrays769B.8PracticalAspects771B.8.1MOSFETFabricationandBehavior771B.8.2MOSFETOnResistance775B.8.3VoltageLevelsinLogicGates776B.8.4NoiseMargin778B.8.5DynamicOperationofLogicGates779B.8.6PowerDissipationinLogicGates782B.8.7Passing1sand0sThroughTransistorSwitches784B.8.8TransmissionGates786B.8.9FaninandFanoutinLogicGates788B.8.10TristateDrivers792B.9StaticRandomAccessMemory(SRAM)794B.9.1SRAMBlocksinPLDs797B.10ImplementationDetailsforSPLDs,CPLDs,andFPGAs797B.10.1ImplementationinFPGAs804B.11ConcludingRemarks806B.12ExamplesofSolvedProblems807Problems814References823Answers825Index839A.14.9米利型有限状态机724A.15编写Verilog代码的原则725A.16小结731参考文献731附录B实现技术733 B.1电晶体开关734B.2NMOS逻辑门736B.3CMOS逻辑门739B.3.1逻辑门电路的速度746B.4负逻辑系统747B.5标準晶片749B.5.17400系列标準晶片749B.6可程式逻辑器件753B.6.1可程式逻辑阵列（PLA）754B.6.2可程式阵列逻辑（PAL）757B.6.3PLA和PAL的编程759B.6.4複杂可程式逻辑阵列（CPLDs）761B.6.5现场可程式门阵列764B.7定製晶片、标準单元和门阵列769B.8实践方面771B.8.1MOSFET工艺和行为771B.8.2MOSFET导通电阻775B.8.3逻辑门中的电平值776B.8.4噪声容限778B.8.5逻辑门的动态特性779B.8.6逻辑门的功耗782B.8.7通过电晶体开关传输1和0784B.8.8传输门786B.8.9逻辑门的扇入和扇出788B.8.10三态驱动器792B.9静态随机存取存储器（SRAM）794B.9.1PLD中的SRAM块797B.10SPLD、CPLD和FPGA的实现细节797B.10.1FPGA实现804B.11小结806B.12问题求解案例807习题814参考文献823习题答案825索引839

• 第1册 朗文国际英语教程
• 我的第一本快乐单词书
• 第二版 建筑装饰装修构造
• 第7册 能力拓展练习
• 跨国公司管理第五版
• 数字吧檯
• 第一级B 剑桥少儿英语考试全真试题
• 第二次修正 长春市农业机械管理条例
• 风骚律师第一季
• 第2版 资料库管理系统（翻译版）