整体设计基于 DDR3 的串口传图帧缓存系统设计实现( 四 ) _串口

<= wrfifo_clr;wr_addr_clr <= wrfifo_clr_sync_ui_clk;endalways@(posedge ui_clk)beginrdfifo_clr_sync_ui_clk <= rdfifo_clr;rd_addr_clr <= rdfifo_clr_sync_ui_clk;endfifo2mig_axi#(.WR_DDR_ADDR_BEGIN (0),.WR_DDR_ADDR_END(DISP_WIDTH*DISP_HEIGHT*2 ),.RD_DDR_ADDR_BEGIN (0),.RD_DDR_ADDR_END(DISP_WIDTH*DISP_HEIGHT*2 ),.AXI_ID(4'b0000),.AXI_LEN(8'd31)//axi burst length = 32)fifo2mig_axi(//FIFO Interface ports.wr_addr_clr(wr_addr_clr), //1:clear sync ui_clk.wr_fifo_rdreq(wrfifo_rden),.wr_fifo_rddata(wrfifo_dout),.wr_fifo_empty(wrfifo_empty),.wr_fifo_rd_cnt(wrfifo_rd_cnt),.wr_fifo_rst_busy(wrfifo_wr_rst_busy | wrfifo_rd_rst_busy),.rd_addr_clr(rd_addr_clr), //1:clear sync ui_clk.rd_fifo_wrreq(rdfifo_wren),.rd_fifo_wrdata(rdfifo_din),.rd_fifo_alfull(rdfifo_full),.rd_fifo_wr_cnt(rdfifo_wr_cnt),.rd_fifo_rst_busy(rdfifo_wr_rst_busy | rdfifo_rd_rst_busy),// Application interface ports.ui_clk(ui_clk),.ui_clk_sync_rst(ui_clk_sync_rst),.mmcm_locked(mmcm_locked),.init_calib_complete (init_calib_complete ),// Slave Interface Write Address Ports.m_axi_awid(s_axi_awid),.m_axi_awaddr(s_axi_awaddr),.m_axi_awlen(s_axi_awlen),.m_axi_awsize(s_axi_awsize),.m_axi_awburst(s_axi_awburst),.m_axi_awlock(s_axi_awlock),.m_axi_awcache(s_axi_awcache),.m_axi_awprot(s_axi_awprot),.m_axi_awqos(s_axi_awqos),.m_axi_awvalid(s_axi_awvalid),.m_axi_awready(s_axi_awready),// Slave Interface Write Data Ports.m_axi_wdata(s_axi_wdata),.m_axi_wstrb(s_axi_wstrb),.m_axi_wlast(s_axi_wlast),.m_axi_wvalid(s_axi_wvalid),.m_axi_wready(s_axi_wready),// Slave Interface Write Response Ports.m_axi_bid(s_axi_bid),.m_axi_bresp(s_axi_bresp),.m_axi_bvalid(s_axi_bvalid),.m_axi_bready(s_axi_bready),// Slave Interface Read Address Ports.m_axi_arid(s_axi_arid),.m_axi_araddr(s_axi_araddr),.m_axi_arlen(s_axi_arlen),.m_axi_arsize(s_axi_arsize),.m_axi_arburst(s_axi_arburst),.m_axi_arlock(s_axi_arlock),.m_axi_arcache(s_axi_arcache),.m_axi_arprot(s_axi_arprot),.m_axi_arqos(s_axi_arqos),.m_axi_arvalid(s_axi_arvalid),.m_axi_arready(s_axi_arready),// Slave Interface Read Data Ports.m_axi_rid(s_axi_rid),.m_axi_rdata(s_axi_rdata),.m_axi_rresp(s_axi_rresp),.m_axi_rlast(s_axi_rlast),.m_axi_rvalid(s_axi_rvalid),.m_axi_rready(s_axi_rready));mig_7series_0 u_mig_7series_0 (// Memory interface ports.ddr3_addr(ddr3_addr),// output [13:0]ddr3_addr.ddr3_ba(ddr3_ba),// output [2:0]ddr3_ba.ddr3_cas_n(ddr3_cas_n),// outputddr3_cas_n.ddr3_ck_n(ddr3_ck_n),// output [0:0]ddr3_ck_n.ddr3_ck_p(ddr3_ck_p),// output [0:0]ddr3_ck_p.ddr3_cke(ddr3_cke),// output [0:0]ddr3_cke.ddr3_ras_n(ddr3_ras_n),// outputddr3_ras_n.ddr3_reset_n(ddr3_reset_n),// outputddr3_reset_n.ddr3_we_n(ddr3_we_n),// outputddr3_we_n.ddr3_dq(ddr3_dq),// inout [15:0]ddr3_dq.ddr3_dqs_n(ddr3_dqs_n),// inout [1:0]ddr3_dqs_n.ddr3_dqs_p(ddr3_dqs_p),// inout [1:0]ddr3_dqs_p.init_calib_complete(init_calib_complete ),// outputinit_calib_complete.ddr3_cs_n(ddr3_cs_n),// output [0:0]ddr3_cs_n.ddr3_dm(ddr3_dm),// output [1:0]ddr3_dm.ddr3_odt(ddr3_odt),// output [0:0]ddr3_odt// Application interface ports.ui_clk(ui_clk),// outputui_clk.ui_clk_sync_rst(ui_clk_sync_rst),// outputui_clk_sync_rst.mmcm_locked(mmcm_locked),// outputmmcm_locked.aresetn(aresetn),// inputaresetn.app_sr_req(1'b0),// inputapp_sr_req.app_ref_req(1'b0),// inputapp_ref_req.app_zq_req(1'b0),// inputapp_zq_req.app_sr_active(),// outputapp_sr_active.app_ref_ack(),// outputapp_ref_ack.app_zq_ack(),// outputapp_zq_ack// Slave Interface Write Address Ports.s_axi_awid(s_axi_awid),// input [3:0]s_axi_awid.s_axi_awaddr(s_axi_awaddr),// input [27:0]s_axi_awaddr.s_axi_awlen(s_axi_awlen),// input [7:0]s_axi_awlen.s_axi_awsize(s_axi_awsize),// input [2:0]s_axi_awsize.s_axi_awburst(s_axi_awburst),// input [1:0]s_axi_awburst.s_axi_awlock(s_axi_awlock),// input [0:0]s_axi_awlock.s_axi_awcache(s_axi_awcache),// input [3:0]s_axi_awcache.s_axi_awprot(s_axi_awprot),// input [2:0]s_axi_awprot.s_axi_awqos(s_axi_awqos),// input [3:0]s_axi_awqos.s_axi_awvalid(s_axi_awvalid),// inputs_axi_awvalid.s_axi_awready(s_axi_awready),// outputs_axi_awready// Slave Interface Write Data Ports.s_axi_wdata(s_axi_wdata),// input [127:0]s_axi_wdata.s_axi_wstrb(s_axi_wstrb),// input [15:0]s_axi_wstrb.s_axi_wlast(s_axi_wlast),// inputs_axi_wlast.s_axi_wvalid(s_axi_wvalid),// inputs_axi_wvalid.s_axi_wready(s_axi_wready),// outputs_axi_wready// Slave Interface Write Response Ports.s_axi_bid(s_axi_bid),// output [3:0]s_axi_bid.s_axi_bresp(s_axi_bresp),// output [1:0]s_axi_bresp.s_axi_bvalid(s_axi_bvalid),// outputs_axi_bvalid.s_axi_bready(s_axi_bready),// inputs_axi_bready// Slave Interface Read Address Ports.s_axi_arid(s_axi_arid),// input [3:0]s_axi_arid.s_axi_araddr(s_axi_araddr),// input [27:0]s_axi_araddr.s_axi_arlen(s_axi_arlen),// input [7:0]s_axi_arlen.s_axi_arsize(s_axi_arsize),// input [2:0]s_axi_arsize.s_axi_arburst(s_axi_arburst),// input [1:0]s_axi_arburst.s_axi_arlock(s_axi_arlock),// input [0:0]s_axi_arlock.s_axi_arcache(s_axi_arcache),// input [3:0]s_axi_arcache.s_axi_arprot(s_axi_arprot),// input [2:0]s_axi_arprot.s_axi_arqos(s_axi_arqos),// input [3:0]s_axi_arqos.s_axi_arvalid(s_axi_arvalid),// inputs_axi_arvalid.s_axi_arready(s_axi_arready),// outputs_axi_arready// Slave Interface Read Data Ports.s_axi_rid(s_axi_rid),// output [3:0]s_axi_rid.s_axi_rdata(s_axi_rdata),// output [127:0]s_axi_rdata.s_axi_rresp(s_axi_rresp),// output [1:0]s_axi_rresp.s_axi_rlast(s_axi_rlast),// outputs_axi_rlast.s_axi_rvalid(s_axi_rvalid),// outputs_axi_rvalid.s_axi_rready(s_axi_rready),// inputs_axi_rready// System Clock Ports.sys_clk_i(loc_clk200m),.sys_rst(mig_reset_n)// input sys_rst);endmodule

整体设计 基于 DDR3 的串口传图帧缓存系统设计实现( 四 )

整体设计基于 DDR3 的串口传图帧缓存系统设计实现( 四 )