整体设计基于 DDR3 的串口传图帧缓存系统设计实现( 三 ) _串口

<= 16'd0;// else if(!init_calib_complete)// col_data_cnt <= 16'd0;// else if(col_data_cnt == DISP_WIDTH*2)// col_data_cnt <= 16'd0;// else// col_data_cnt <= col_data_cnt + 1'b1;// end// always@(posedge loc_clk50m or posedge ui_clk_sync_rst)// begin// if(ui_clk_sync_rst)// row_data_cnt <= 16'd0;// else if(col_data_cnt == DISP_WIDTH*2)// if(row_data_cnt >= DISP_HEIGHT-1)// row_data_cnt <= 16'hffff;// else// row_data_cnt <= row_data_cnt + 1'b1;// else// row_data_cnt <= row_data_cnt;// end// assign uart_byte = row_data_cnt[7:0];// assign uart_byte_vaild = (col_data_cnt == DISP_WIDTH*2);//-------------------------------------------wire [15:0]image_data;wireimage_data_valid;reg [15:0] image_data_hcnt;reg [15:0] image_data_vcnt;regimage_data_hs;regimage_data_vs;bit8_trans_bit16 bit8_trans_bit16(.clk(loc_clk50m),.reset_p(ui_clk_sync_rst ),.bit8_in(uart_byte),.bit8_in_valid(uart_byte_vaild ),.bit16_out(image_data),.bit16_out_valid (image_data_valid));//-------------------------------------------------------------------------------------------//generate image data hs or vs观察数据是否产生了800*480always@(posedge loc_clk50m or posedge ui_clk_sync_rst)if(ui_clk_sync_rst)image_data_hcnt <= 'd0;else if(image_data_valid) beginif(image_data_hcnt == (DISP_WIDTH - 1'b1))image_data_hcnt <= 'd0;elseimage_data_hcnt <= image_data_hcnt + 1'b1;endalways@(posedge loc_clk50m or posedge ui_clk_sync_rst)if(ui_clk_sync_rst)image_data_vcnt <= 'd0;else if(image_data_valid) beginif(image_data_hcnt == (DISP_WIDTH - 1'b1)) beginif(image_data_vcnt == (DISP_HEIGHT - 1'b1))image_data_vcnt <= 'd0;elseimage_data_vcnt <= image_data_vcnt + 1'b1;endend//hsalways@(posedge loc_clk50m or posedge ui_clk_sync_rst)if(ui_clk_sync_rst)image_data_hs <= 1'b0;else if(image_data_valid && image_data_hcnt == (DISP_WIDTH - 1'b1))image_data_hs <= 1'b0;elseimage_data_hs <= 1'b1;//vsalways@(posedge loc_clk50m or posedge ui_clk_sync_rst)if(ui_clk_sync_rst)image_data_vs <= 1'b0;else if(image_data_valid && image_data_hcnt == (DISP_WIDTH - 1'b1) &&image_data_vcnt == (DISP_HEIGHT - 1'b1))image_data_vs <= 1'b0;elseimage_data_vs <= 1'b1;always@(posedge loc_clk50m or posedge ui_clk_sync_rst)if(ui_clk_sync_rst)frame_rx_done_flip <= 1'b0;else if(image_data_valid && image_data_hcnt == (DISP_WIDTH - 1'b1) &&image_data_vcnt == (DISP_HEIGHT - 1'b1))frame_rx_done_flip <= ~frame_rx_done_flip;//-------------------------------------------------------------------------------------------assign wrfifo_din= image_data;assign wrfifo_wren = image_data_valid;disp_driver disp_driver(.ClkDisp(clk_disp),.Rst_p(ui_clk_sync_rst),.Data(rdfifo_dout),.DataReq(rdfifo_rden),.Disp_HS(TFT_hs),.Disp_VS(TFT_vs),.Disp_Red(TFT_rgb[15:11] ),.Disp_Green(TFT_rgb[10:5]),.Disp_Blue(TFT_rgb[4:0]),.Frame_Begin (frame_begin),.Disp_DE(TFT_de),.Disp_PCLK(TFT_clk));assign TFT_pwm = 1'b1;assign wrfifo_clr = ui_clk_sync_rst;assign rdfifo_clr = frame_begin || ui_clk_sync_rst;wr_ddr3_fifo wr_ddr3_fifo(.rst(wrfifo_clr), // inputwire rst.wr_clk(loc_clk50m), // inputwire wr_clk.rd_clk(ui_clk), // inputwire rd_clk.din(wrfifo_din), // inputwire [15 : 0] din.wr_en(wrfifo_wren), // inputwire wr_en.rd_en(wrfifo_rden), // inputwire rd_en.dout(wrfifo_dout), // output wire [127 : 0] dout.full(), // output wire full.empty(wrfifo_empty), // output wire empty.rd_data_count (wrfifo_rd_cnt), // output wire [5 : 0] rd_data_count.wr_data_count (), // output wire [8 : 0] wr_data_count.wr_rst_busy(wrfifo_wr_rst_busy ), // output wire wr_rst_busy.rd_rst_busy(wrfifo_rd_rst_busy )// output wire rd_rst_busy);rd_ddr3_fifo rd_ddr3_fifo(.rst(rdfifo_clr), // input wire rst.wr_clk(ui_clk), // input wire wr_clk.rd_clk(loc_clk33m), // input wire rd_clk.din(rdfifo_din), // input wire [127 : 0] din.wr_en(rdfifo_wren), // input wire wr_en.rd_en(rdfifo_rden), // input wire rd_en.dout(rdfifo_dout), // output wire [15 : 0] dout.full(rdfifo_full), // output wire full.empty(), // output wire empty.rd_data_count (), // output wire [8 : 0] rd_data_count.wr_data_count (rdfifo_wr_cnt), // output wire [5 : 0] wr_data_count.wr_rst_busy(rdfifo_wr_rst_busy ), // output wire wr_rst_busy.rd_rst_busy(rdfifo_rd_rst_busy )// output wire rd_rst_busy);always@(posedge ui_clk)beginwrfifo_clr_sync_ui_clk

整体设计 基于 DDR3 的串口传图帧缓存系统设计实现( 三 )

整体设计基于 DDR3 的串口传图帧缓存系统设计实现( 三 )