整个系统所需的 IP 已经创建完成，创建的 IP 可以通过在窗口的 IP中看
到 。可鼠标双击进行修改配置等操作 。
四、模块
该模块主要作用是串联其他模块，完成传图过程 。其中个模块对应的介绍均在第二节后附有连接，以供参考 。
/// Module Name: uart_ddr3_tft// Description: 串口传图DDR3缓存TFT屏显示// Version: Vivado2018.3 // Name: 小王在努力.../module uart_ddr3_tft(//System clock resetinputclk50m, //系统时钟输入,50MHzinputreset_n, //复位信号输入//LEDoutput [3:0]led,//Uart interfaceinputuart_rx, //串口输入信号//TFT Interfaceoutput [15:0]TFT_rgb, //TFT数据输出outputTFT_hs, //TFT行同步信号outputTFT_vs, //TFT场同步信号outputTFT_clk, //TFT像素时钟outputTFT_de, //TFT数据使能outputTFT_pwm, //TFT背光控制//DDR3 Interface// Inoutsinout[15:0]ddr3_dq,inout[1:0]ddr3_dqs_n,inout[1:0]ddr3_dqs_p, // Outputsoutput [13:0]ddr3_addr,output [2:0]ddr3_ba,outputddr3_ras_n,outputddr3_cas_n,outputddr3_we_n,outputddr3_reset_n,output [0:0]ddr3_ck_p,output [0:0]ddr3_ck_n,output [0:0]ddr3_cke,output [0:0]ddr3_cs_n,output [1:0]ddr3_dm,output [0:0]ddr3_odt);//*********************************//Internal connect//*********************************//clockwirepll_locked;wireloc_clk50m;wireloc_clk200m;wireloc_clk33m;wireloc_clk9m;//uart Interfacewire [7:0]uart_byte;wireuart_byte_vaild;//wr_fifo Interfacewire [15:0]wrfifo_din;wirewrfifo_wren;wirewrfifo_rden;wire [127:0]wrfifo_dout;wire [5 : 0]wrfifo_rd_cnt;wirewrfifo_empty;wirewrfifo_wr_rst_busy;wirewrfifo_rd_rst_busy;//rd_fifo Interfacewirerdfifo_wren;wire [127:0]rdfifo_din;wirerdfifo_rden;wire [15 :0]rdfifo_dout;wire [5 : 0]rdfifo_wr_cnt;wirerdfifo_full;wirerdfifo_wr_rst_busy;wirerdfifo_rd_rst_busy;//mig Interface wiremig_reset_n;wirearesetn;wiremmcm_locked;wireinit_calib_complete;wireui_clk;wireui_clk_sync_rst;wire[3:0]s_axi_awid;wire[27:0]s_axi_awaddr;wire[7:0]s_axi_awlen;wire[2:0]s_axi_awsize;wire[1:0]s_axi_awburst;wire[0:0]s_axi_awlock;wire[3:0]s_axi_awcache;wire[2:0]s_axi_awprot;wire[3:0]s_axi_awqos;wires_axi_awvalid;wires_axi_awready;wire[127:0]s_axi_wdata;wire[15:0]s_axi_wstrb;wires_axi_wlast;wires_axi_wvalid;wires_axi_wready;wire [3:0]s_axi_bid;wire [1:0]s_axi_bresp;wires_axi_bvalid;wires_axi_bready;wire[3:0]s_axi_arid;wire[27:0]s_axi_araddr;wire[7:0]s_axi_arlen;wire[2:0]s_axi_arsize;wire[1:0]s_axi_arburst;wire[0:0]s_axi_arlock;wire[3:0]s_axi_arcache;wire[2:0]s_axi_arprot;wire[3:0]s_axi_arqos;wires_axi_arvalid;wires_axi_arready;wire [3:0]s_axi_rid;wire [127:0]s_axi_rdata;wire [1:0]s_axi_rresp;wires_axi_rlast;wires_axi_rvalid;wires_axi_rready;//tftwireclk_disp;wireframe_begin;wirerdfifo_clr;regrdfifo_clr_sync_ui_clk;regrd_addr_clr;wirewrfifo_clr;regwrfifo_clr_sync_ui_clk;regwr_addr_clr;regframe_rx_done_flip;//兼容TFT5.0寸和TFT4.3寸显示屏,可根据实际进行配置选择/*parameter DISP_WIDTH= 480;parameter DISP_HEIGHT = 272;assign clk_disp = loc_clk9m;*/parameter DISP_WIDTH= 800;parameter DISP_HEIGHT = 480;assign clk_disp = loc_clk33m;assign mig_reset_n = pll_locked;assign aresetn= pll_locked;assign led = {frame_rx_done_flip,init_calib_complete,mmcm_locked,pll_locked};pll pll(// Clock out ports.clk_out1 (loc_clk50m), // output clk_out1.clk_out2 (loc_clk200m), // output clk_out2.clk_out3 (loc_clk33m), // output clk_out3.clk_out4 (loc_clk9m), // output clk_out4// Status and control signals.resetn(reset_n), // input reset.locked(pll_locked), // output locked// Clock in ports.clk_in1(clk50m)// input clk_in1);uart_byte_rx#(.CLK_FRQ(1000000000))uart_byte_rx(.clk(loc_clk50m),.reset_p(ui_clk_sync_rst),.baud_set (3'd5), //1562500bps.uart_rx(uart_rx),.data_byte(uart_byte),.rx_done(uart_byte_vaild )//一个字节数据有效的标志);//---------------------------------------------//仅仿真用,正常功能时,将197~226行代码屏蔽//仿真时,取消屏蔽197~226行代码,将179~191代码屏蔽//---------------------------------------------// reg [15:0]col_data_cnt;// reg [15:0]row_data_cnt;// always@(posedge loc_clk50m or posedge ui_clk_sync_rst)// begin// if(ui_clk_sync_rst)// col_data_cnt